1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device of the type manufactured by a master slice method. More specifically, the present invention relates to an MOS type large scale integration of a gate array.
2. Description of the Prior Art
An example of a semiconductor integrated circuit device of a master slice method is disclosed in, for example, Japanese Utility Model Publication Gazette No. 44592/1983, wherein an aggregation of elementary units each normally including an elementary circuit including a plurality of transistors and resistors is first formed in on a mass production basis in a single semiconductor piece or chip, and a connection mask is later fabricated depending on a line of products to be developed, so that any necessary transistors and resistors may be interconnected to provide a large scale integration having a desired electrical circuitry operation.
Since an aggregation of elementary units including transistors and resistors is formed a head of time on a mass production basis, it is sufficient to fabricate only a mask for a connection whenever a desire arises that a new line of products be developed, thereby to shorten a period of development. Furthermore, since an aggregation of elementary units can be commonly used to a variety of large scale integrations, a development cost is reduced.
It has been a general practice that such large scale integration of a master slice method is formed in a regular matrix type arrangement in a desired region of a semiconductor chip of an aggregation of elementary units including transistors and resistors and such standardization makes it possible to effectively employ an automatic arrangement and connection processing through a computer aided design by the use of a computer.
However, it is seldom that a resistive element becomes necessary at every elementary unit in such semiconductor integrated circuit, inasmuch as such resistive elements become necessary only in a particular case of such as an RC delay circuit, a circuit for suppressing a DC current, and so on. Accordingly, provision of a resistive element in every elementary unit leads to an increase in unnecessary area and results in a large size of a whole chip or reduction of the number of transistors contained in the same chip area, with the resultant limits to enhancement of the degree of integration.